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Design, fabrication and evaluation of silicon tip chips for reverse tip sample scanning probe microscopy

Giulia Scamporrino

Design, fabrication and evaluation of silicon tip chips for reverse tip sample scanning probe microscopy.

Rel. Matteo Cocuzza. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2021

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Abstract:

Recently, a new and promising scanning probe microscopy (SPM) configuration called reverse tip sample (RTS) SPM has been developed at IMEC to overcome the main limitations of the classical SPM approach. In RTS SPM, the classical position of tip and sample is switched: the tip is placed on the stage (where normally the sample is located) and the sample is placed at the cantilever end (where the tip is commonly located). The major advantage of this novel approach is the possibility to substitute a single tip with a chip containing hundreds to thousands of tips. Further advantages of this promising method are: rapid and seamless tip switching within seconds (typically 10 min in the classical configuration), the potential to combine different measurement techniques requiring each a different tip and measure quasi simultaneously with different tips for improved data statistics. So far, only pyramidal diamond tips made by the common moulding approach have been developed and used for RTS SPM. Despite their high hardness and suitable sharpness, they suffer from a low aspect ratio and are not well suited for all SPM modes. Furthermore, the moulding process is not easily adaptable to other attractive tip materials such as silicon and metals. Therefore, the main aim of this thesis project is to design, fabricate and evaluate various silicon RTS tip chips prototypes with a focus on high-aspect-ratio tips and the selection of a technology approach adaptable to other tip materials. For this, the tips geometrical requirements are first analysed and established and a suitable tip chip layout is determined. Next, a manufacturing process based mainly on lithography and dry etching is developed, the silicon RTS tip chips are fabricated and subsequently inspected. Through iterative cycles the process parameters are optimized and improved bringing the tip prototype features closer to the required specifications. Finally, the RTS tip chips functionality and performances are validated through SPM measurements in RTS mode.

Relatori: Matteo Cocuzza
Anno accademico: 2020/21
Tipo di pubblicazione: Elettronica
Numero di pagine: 89
Soggetti:
Corso di laurea: Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Ente in cotutela: Interuniversity Microelectronics Centre (IMEC) (BELGIO)
Aziende collaboratrici: IMEC
URI: http://webthesis.biblio.polito.it/id/eprint/17880
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