Parameter Monitoring and Communication in a Ring-Topology-Based SNN Emulator Hardware.

The work of this thesis is focused on the extraction and distribution of internalparameters belonging to the HEENS architecture, which is a scalable Spiking Neural Network emulator. All of the projects are developed by means of the VHDL description, then simulated through the Questa Sim Advanced Simulator and finally synthesized and implemented on a Programmable System on Chip (PSOC), in order to verify time constraints and resources exploitation. In more details, the additions and improvements made to the architecture concern the array of Processing Elements and especially those modules relative to the Address Event Representation over Synchronous Serial Ring Topology, all previously developed by the Integrated Smart Sensors and Health Technologies (ISSET) research group from the Universitat Politècnica de Catalunya (UPC). The AER-SRT blocks are used to support a serial communication between different FPGA of the network. After the first monitoring implementation had been designed and verified, the following step of the work was to improve performances, through a better exploitation of the PE-array parallel nature (it is a Single Instruction Multiple Data architecture) and by means of an hardware enhancement, since the first implementation did not represent a critical part from an area occupancy point of view. The multi-board version has been implemented on a 5x5 array configuration, while the single-board has been tested on a 13x13 architecture.