Nowadays, with he increase of the complexity of system on chips SOC, the ASIC industry struggles to meet schedules of time to market TTM. System on chips market is complex in term of the business and technology point of view. However, the time to market enforces a huge pressure to this industry. As a consequence of these factors: appearance of new challenges, among them the top one which is verification. This last one consumes more than 70 percent of design effort. In 1999,Vertual Socket Alliance (VSIA) held a workshop, with the aim of discussing the verification challenges for the new ASIC architecture, the conclusion of this workshop that gathered only the experts of verification in the world was verification is hard.