Machine Learning for the generation of vias in Integrated Circuits

Integrated circuits are at the core of the electronic systems. They deliver the functionality of the system within the design envelope for power, performance and form factor. A typical IC consists of multiple layers of metal and polysilicon which are interconnected by electrical connections called vias. In IC fabrication, vias can be generated wherever two or more conductive layers overlap. However, via generation is bound by certain constraints that need not be violated. In today’s competitive market, all the major semiconductor and systems companies need to have unique features in their design that should stand out in the market. For this reason, every company has its own set of constraints. The current heuristic algorithm used for via generation - called AutoVia - is proving to be slow for very large scale designs. The idea of this internship was to develop a machine learning-based approach towards via creation. The results provided by the thesis give a very good starting point for a machine learning-based approach for via generation, as it performed very well on all the metrics against the traditional heuristic approach. If this approach is pursued further, it has the potential to replace the heuristic approach completely in future designs.