Design of the execution pipeline for LEN5, an out-of-order RISC-V processor
Michele Caon
Design of the execution pipeline for LEN5, an out-of-order RISC-V processor.
Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019
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Abstract
Design of a RISC-V out-of-order, multiple issue, general purpose processor, with support for an operating system and possibly other ISA defined extensions. The project will be developed and documented on GitHub.
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