Computing architectures based on skyrmions

In this thesis are addressed the issues linked to the realization and use of logic gates based on skyrmions. In the first chapter is offered a general overview about the main physical phenomena involved in the nucleation, the movement and the detection of skyrmions. Some applicative aspects, that can either be useful to better understand the practical meaning of some physical properties, or that can be helpful in solving the main issues, are presented as well. In the second chapter is analysed, by means of micromagnetic simulations, the behaviour of a particular type of skyrmionic logic gate that can be found in literature. The study is performed by imposing a realistic current density distribution inside the gate, using the software COMSOL Multiphysics together with mumax3. The characteristic parameters of both the AND/OR gate and of the NOT/COPY gate are tuned in order to improve the performances and to reduce the energetic inefficiencies. In the third chapter the logic gates already analysed are used to build a generic N bit ripple-carry adder. The structure of the adder is organized to minimize the energetic consumption due to the need of nucleating skyrmions that are necessary for performing the computation, but are not useful as information carriers. The adder is described in VHDL and simulated for analysing its performances, while assuming for the physical and technological parameters values that are compatible with the micromagnetic simulations performed in the second chapter. In the fourth chapter is studied a possible realization of logic in memory based on skyrmions, starting from an example of logic in memory based on CMOS technology already presented in literature. The corresponding skyrmionic architecture inherits from the original version the great flexibility and adaptability to the algorithm, and adds also a mechanism for the reuse of all the skyrmions already nucleated, in order to minimize the energetic inefficiency. The resulting structure, however, is very complex and not optimized: for this reason is proposed also a second architecture, less flexible but lighter and faster. Both structures are described in VHDL and verified through simulations.