Implementation of neural networks systems on FPGA for feature detection

This report presents the results of the work done for the Fasteye camera project inside CSEM. The overall camera system is depicted in Figure 1. The image (or video) captured by the sensor is transferred to the FPGA board which processes the data and feeds them into the external, main memory. From the latter the data are then moved through the USB interface toward the USB connector, and eventually to a peripheral device (e.g., a laptop). The main aim was to create a reliable, generic interface between the sensor interface) and the FINN accelerator block within the Datapath. FINN, which had already been implemented inside the system, is a framework for building fast, scalable Binarized Neural Network inference accelerators on FPGA. The addition of a neural network to the camera is motivated by the possibility to create an extremely fast feature recognition tool for images and video recordings, which allows for interesting applications such as material defects detection. The aforementioned interface is intended to feed the FINN with meaningful data. As an additional goal, the work aimed at making the existing k325-mercury enclustra-based framework compatible with a simpler FPGA system (k160-mercury board), adding new features and without losing the preexistent functionalities. A version for the k160 board was already been developed, but with less features. Results of the implementation are presented in the last section.