Optimization and Acceleration of 5G Link Layer Simulator

Requirements for higher data rates and wider bandwidth are increasing day by day with the rise and number of digital devices. Modern digital devices and systems such as IoT, autonomous vehicles, smartphones, entertainment systems require a good data rate and quality service. LTE was presented as a successor of 4G to fulfill this requirement, but it is getting more and more congested with a rapid rise in a number of connected devices and bandwidth requirements. To address these challenges, 3GPP announced the specification of a 5G network that will overcome all these issues and provide higher data rates and wider bandwidth by using higher frequencies. This architecture uses millimeter waves instead of frequencies used up to 4G. The frequency range for millimeter waves is from 30 to 300GHz. The problem with millimeter waves is that they are absorbed and dispersed easily by obstacles and thus can travel less distance. To overcome this issue, base stations need to be spaced closely. This results in a higher number of antennas spaced closely to each other. When using higher data rates and a large number of antennas, parameter tracking becomes computationally more and more complex. These parameters include angle of arrival(AoA), angle of departure(AoD), Zenith Angles of Arrival(ZOA) with Zenith Angles of Departure(ZOD), user speed, user direction, antenna correlation. Each time these parameters change, the channel needs to reconfigure its parameters. The case is even more complex for an object moving with high speed. This results in performance degradation due to this bottleneck. This work focuses on optimization and acceleration of parameter tracking, calculation, and reconfiguration for a 5G channel model. Parameter tracking and re-calculation requires high computation time and a large amount of memory. Conventionally, FPGAs are programmed using HDL-based design methodology to accelerate computationally intense applications. FPGAs are frequently used in many real-world applications to speed up the performance alongside lower power consumption as compared to GPUs and multi-core CPUs. The OpenCL Synthesis tools for Xilinx and Intel FPGAs enable us to accelerate applications with short development time. This thesis presents an optimized implementation of a 5G NR(New-Radio) link-layer simulation model using OpenCL. Performance and power consumption for CPU and FPGA platform is presented for various dimensions of the kernel.