Hybrid on-line self-test architecture for computational units on embedded processor cores

Safety-critical applications require reaching high fault coverage figures for on-line testing in order to be compliant with functional safety standards currently in use. In the present days, in order to meet such strict requirements, different solutions are adopted by semiconductor manufactures. The range of applied approaches may vary from pure hardware-based mechanisms to software-based ones. Each of these possible solutions presents both advantages and drawbacks. Typically: software approaches are less intrusive and have the advantage of reduced test application time compared to hardware ones. Conversely, although hardware approaches are normally invasive and have longer test application time, they also yield high defect coverage. This thesis aims to suggest an innovative Design for Test infrastructure, accessible via software, for enabling a high fault coverage on-line test of arithmetic units within embedded processor cores. The end-goal of this alternative design is to overcome limitations of both hardware and software-based test approaches, while striving for a low invasive on-line test. Such architecture was implemented on an open source processor, the OpenRISC 1200 and its effectiveness evaluated by means of exhaustive fault injection campaigns.