Gianmarco Mongano
Hybrid on-line self-test architecture for computational units on embedded processor cores.
Rel. Edgar Ernesto Sanchez Sanchez, Davide Piumatti, Andrea Floridia. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019
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Abstract
Safety-critical applications require reaching high fault coverage figures for on-line testing in order to be compliant with functional safety standards currently in use. In the present days, in order to meet such strict requirements, different solutions are adopted by semiconductor manufactures. The range of applied approaches may vary from pure hardware-based mechanisms to software-based ones. Each of these possible solutions presents both advantages and drawbacks. Typically: software approaches are less intrusive and have the advantage of reduced test application time compared to hardware ones. Conversely, although hardware approaches are normally invasive and have longer test application time, they also yield high defect coverage.
This thesis aims to suggest an innovative Design for Test infrastructure, accessible via software, for enabling a high fault coverage on-line test of arithmetic units within embedded processor cores
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