Optimization techniques for address translation caches

Most modern microprocessor architectures use virtual memory as an abstraction of physical memory to make programs position independent and isolated from each other. While effective, this technique brings a lot of execution overhead, since each memory access needs to be handled by a series of memory lookups, that are by themselves quite slow already. For this reason, a cache-like structure called Translation Lookaside Buffer (TLB) is employed to accelerate virtual-to-physical address translation. It is well known that TLBs have a big impact on system performance, and a great amount of research has already been performed in order to optimize their effectiveness. This work starts by presenting various techniques already proposed in literature. After investigating their effectiveness in real-world applications, an exhaustive survey about the state of the art will be proposed, focusing on respective pros and cons, and the reason why some are better than others. Thanks to the natural contiguity generated by the standard OS memory allocator, a CPU can exploit the locality of allocated pages to create more effective TLB structures. After showing the various possibilities, this study focuses in particular on clustering, a technique that is able to group various TLB entries into a single one. Moreover, my research brought a new technique to life, called decoupled clustering, that further enhances the benefits of clustering by increasing the reach capability on Physical Addresses. Finally, some insight will be provided about the implementation and challenges of such techniques, both on a software-based CPU model and at the Register Transfer Level, used in the physical implementation of next-generation Arm microprocessors.