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Thesis by Valente, Simone

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Thesis

Simone Valente. Generalized UVM testbench framework for verification of eFPGA devices. Rel. Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

This list was generated on Tue May 14 08:46:16 2024 CEST.