Study and Implementation of a Packet Video Transmission Wireless Receiver

In recent years mobile radio communication systems have become increasingly important thanks to their pervasiveness, attracting interest and going through constant changes to keep up with technological development and user demands. Characterized by ever higher date rates (up to tens of Gbps) it is important to ensure speed and reliability at the lowest possible cost. The use of Orthogonal Frequency-Division Multiplexing (OFDM) digital transmission gives the opportunity to encode data on multiple carrier frequencies, thus allowing to broadcast data in parallel. Additionally, compared to the single carrier systems, it introduces a series of advantages, such as immunity to selective fading and spectrum efficiency, that makes its use very common in many existing high data-rate standards, e.g. DVB-T and WLAN. Livetools Technology SA is a Swiss company specialized in the production of portable digital transmitters and receivers intended for wireless cameras and TV production systems. In the last few years, in partnership with the REDS institute, experts in high-performance embedded systems, they have conceived a new communication protocol closely shaped for short-range communication in an indoor scenario, allowing a bi-directional and asymmetrical packet-based communication between devices. Given that the communication is packet-based, the synchronizer becomes a key element of the receiver. It deals with the frame's detection and correction, two aspects that strongly influence the system performance. The main aim of this work is designing the receiver's synchronization stage for this new communication protocol. Starting from the C++ simulation model of the complete transmission chain, composed by both modulator and demodulator, a performance analysis is carried out to find out which modification allows to obtain the same BER performance that the chain would have in case of ideal synchronization. The second part of this work is focused on the VHDL implementation of the synchronizer, where the best solutions in terms of latency and used area are implemented, to best fit the FPGA's available resources. By changing the composition of the frame, in particular the preamble part, and integrating additional features that can help the demodulation phase, it is possible to obtain a synchronizer that respects all the imposed constraints and does not introduce performance losses.