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Modeling of RISC-V Exceptions for Hardware Code Generation

Matteo Zappia

Modeling of RISC-V Exceptions for Hardware Code Generation.

Rel. Danilo Demarchi, Daniel Muller-Gritschneder. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018

Abstract:

Generating exception behavior in RTL and VP
Relators: Danilo Demarchi, Daniel Muller-Gritschneder
Academic year: 2018/19
Publication type: Electronic
Number of Pages: 83
Additional Information: Tesi secretata. Fulltext non presente
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: Technische Universität München (GERMANIA)
Aziende collaboratrici: Infineon Technologies AG
URI: http://webthesis.biblio.polito.it/id/eprint/9815
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