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Key Management Unit for RISC-V Secure Processor

Fabio Castagno

Key Management Unit for RISC-V Secure Processor.

Rel. Andrea Calimera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018

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Nowadays many embedded applications need to be secure and demand low power operations. The power consumption of designs varies with the implementation choices made by designers. Speed increasing is a key parameters for today’s processor but usually this means more power consumption. A trade-off between these 2 parameters must be found. This work involves the development of the Key Management Unit (KMU) based on a new PUF module. This component is responsible for the generation and distribution of the cryptographic keys. Security services based on cryptographic mechanisms assume cryptographic keys to be distributed to the communicating parties prior to secure communications. The secure management of these keys is one of the most critical elements when integrating cryptographic functions into a system, since even the most elaborate security concept will be ineffective if the key management is weak. Trusted Execution Environments are quickly becoming a preferred method for providing isolation between secure and non-secure execution environments. The protection of these environments, as well as their software structure, is still a primary area of interest and research. The ability to use a Physically Unclonable Function to generate a unique-per-device AES key provides an excellent mechanism for protection of a Trusted Execution Environment at rest through encryption. These keys can also be used to manage modification of the TEE during execution. A physically unclonable function (PUF) circuit extracts unique identification data from device variability, and it is an important technology for authentication and cryptographic key generation, as a countermeasure against counterfeiting of devices, etc. An analysis of different implementation choices with different constraints is made. The energy results are compared to evaluate the savings as well as the latency and area. We prototype our design on NEXYS 4 DDR FPGA. Results show up-to 89% dynamic energy reduction in design with a saving in area.

Relators: Andrea Calimera
Academic year: 2018/19
Publication type: Electronic
Number of Pages: 90
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: Nanyang Technological University (SINGAPORE)
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/9561
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