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Analysis and extension of an open-source VHDL model of a general-purpose GPU

Roascio, Gianluca

Analysis and extension of an open-source VHDL model of a general-purpose GPU.

Rel. Matteo Sonza Reorda, Luca Sterpone, Boyang Du. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2018

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In the last years, high-performance computing requirements leaded to unite the advantages brought by parallel computing typical of graphic processors with the flexibility of the general-purpose programming. This is how the so-called GPGPUs (General-Purpose Graphic Processing Units) have started to be developed and diffused on the market. However, due to their rigid microarchitectural features, GPGPUs are not available as support unit for most of the computing systems. On the contrary, FPGAs (Field Programmable Gate Array) are can be seen as soft (reconfigurable) hardware accelerators to be placed next to CPUs, because they are perfectly adaptable to the designer requirements. Although, when using FPGAs a certain degree of expertise in HDL (Hardware Description Language) coding is expected, and besides, reconfiguration of the logic may take unaffordable times. In order to put together the pros of the two platforms alleviating their drawbacks, University of Massachusetts has studied a model for a soft integer GPGPU optimized for FPGA implementation which is called FlexGrip (FLEXible GRaphIc Processor). Beyond the benefits of using it as an accelerator for FPGA, FlexGrip also has the trivial but not obvious merit of offering the academic community an open-source model of a graphic processor, due to the reservation adopted by GPU manufacturer about the implementation details of their devices. The accelerated development that some sectors of the industry have known in the last years from the automation point of view (think for example of the automotive industry) necessarily pushes companies to request that these components have a sufficiently high degree of reliability. The challenge is gathered by the departments and the academic teams involved in IT reliability, such as ours, which are trying to offer innovative techniques for building efficient SBST (Software-Based Self Test) for such devices. In fact, many of the techniques used routinely for the self-test of normal processors cannot be reused here, due to the presence of specific modules that are to be precisely studied at the gate level to identify all the possible faults. This is clearly not possible without the netlist of a working GPU. Then, this thesis work has been focused on the correction of the VHDL model of FlexGrip through an instruction-level analysis. The behavior of all the nominally supported functionalities has been analyzed by compiling a high number of random CUDA kernels to make appear as many formats as possible of each of the instructions, due to the absence of any reference manual for the effective ISA by Nvidia. Formats which were not fully working or implemented have been corrected and completed, as well as collected in a tool which is able to write down the corresponding mnemonic and binary in the .SASS input file (the format of the assembly language for the Nvidia family).

Relatori: Matteo Sonza Reorda, Luca Sterpone, Boyang Du
Anno accademico: 2018/19
Tipo di pubblicazione: Elettronica
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-32 - INGEGNERIA INFORMATICA
Aziende collaboratrici: NON SPECIFICATO
URI: http://webthesis.biblio.polito.it/id/eprint/9031
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