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Design and characterization of Variable Latency adders for floating-point arithmetic units

Leonardo Pedone

Design and characterization of Variable Latency adders for floating-point arithmetic units.

Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2018

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Abstract:

Studio di architetture a latenza variabile per unità floating-point.
Relators: Maurizio Martina
Academic year: 2017/18
Publication type: Electronic
Number of Pages: 79
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/7439
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