Giulio Milici
Fault tolerant L1 cache for the CORSAIR Multi-Core architecture.
Rel. Alberto Macii. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2018
| Abstract: |
The purpose of the work of this thesis has been to design a fault tolerance system and therefore to find a solution to the presence of soft errors (they are errors not caused by hardware defects and generally have a transitory duration) in the L1 cache of the CORSAIR multi-core architecture, currently under development in the LISAN laboratories of CEA-Leti of Grenoble. |
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| Relators: | Alberto Macii |
| Academic year: | 2017/18 |
| Publication type: | Electronic |
| Number of Pages: | 144 |
| Additional Information: | Tesi secretata. Full text non presente |
| Subjects: | |
| Corso di laurea: | Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering) |
| Classe di laurea: | New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING |
| Ente in cotutela: | CEA-Leti (FRANCIA) |
| Aziende collaboratrici: | CEA-Atomic Energy Commission |
| URI: | http://webthesis.biblio.polito.it/id/eprint/7433 |
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