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System-level Design of a Latency-insensitive RISC-V Microprocessor and Optimization via High-level Synthesis

Robert Margelli

System-level Design of a Latency-insensitive RISC-V Microprocessor and Optimization via High-level Synthesis.

Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2017

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Abstract:

System-level Design of a Latency-insensitive RISC-V Microprocessor and Optimization via High-level Synthesis

Relators: Luciano Lavagno
Academic year: 2017/18
Publication type: Electronic
Number of Pages: 79
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Ente in cotutela: Columbia University (STATI UNITI D'AMERICA)
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/6438
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