Michela Cavigliano
Design and Implementation of a Protocol-Aware Minimal Pinout FPGA-Based Test Controller.
Rel. Paolo Bernardi, Nicola Di Gruttola Giardino, Giorgio Insinga, Annachiara Ruospo. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2026
Abstract
Test access to internal device resources is a fundamental requirement in industrial embedded systems. A flexible and programmable FPGA-based platform can serve as a compact and customizable test controller, representing a building block toward ATE-oriented solutions while integrating into existing proprietary software environments. This thesis focuses on a protocol-aware, minimal pinout FPGA-based test controller for the TC48x microcontroller (Infineon Technologies). The work is structured in two main phases. In the first phase, an existing FPGA-based JTAG access controller was integrated into a proprietary industrial software framework, enabling memory access to the target device. In the second phase, a proprietary two-wire access protocol was studied and implemented on an FPGA.
This work demonstrates that a fully custom FPGA-based test controller can successfully execute proprietary access protocols and operate within an industrial test workflow.
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