In recent years, RISC-V has emerged as a highly attractive Instruction Set Architecture (ISA) thanks to its open standard nature, portability, and modularity. Unlike proprietary ISA, RISC-V enables extensive customization through both standard and custom extensions, making it particularly suitable for specialized domains such as artificial intelligence, aerospace, and defense. Its transparent specification also supports greater hardware inspectability and design trust, which are essential aspects in security- and reliability-critical environments. This thesis presents the design and implementation of a custom RISC-V processor architecture supporting Out-of-Order (OoO) execution and Simultaneous Multithreading (SMT). A central contribution of this work is the integration of a Reorder Buffer (ROB) into the processor pipeline.