Abstract This thesis investigates hardware clock gating as a power-efficiency technique for FPGA- based RISC-V embedded controllers, using the open-source NEORV32 processor as the target architecture. The motivation is the reduction of unnecessary dynamic activity during non-computational intervals, which are common in interrupt-driven embedded systems and UAV-like control workloads. The proposed approach combines the standard RISC-V WFI instruction with a BUFGCE- based gated clock domain implemented on Xilinx Artix-7 FPGAs. At hardware level, the NEORV32 system was modified to introduce a dedicated CPU clock, clk_cpu, whose enable is controlled by the processor sleep state and by the required wake-up sources, including timer and interrupt signals.