Speculative execution is a key contributor to the performance of modern out-of-order processors, but it has been shown to enable transient execution attacks that leak sensitive data through microarchitectural side channels. While software-based mitigations exist, they incur significant performance overheads and provide incomplete protection. Hardware-based defenses offer a more transparent and robust approach, but remain challenging to implement and verify at the register-transfer level. This thesis presents SPT-BOOM, the first register-transfer level (RTL) implementation of Speculative Privacy Tracking (SPT) in an industry-grade superscalar out-of-order processor. SPT is software-transparent protection mechanism against transient execution leakage, which is integrated into BOOMv3, an open-source RISC-V core, and introduces several design adaptations to accommodate architectural constraints and support formal verification.