With increasing digital system complexity and demanding time-to-market requirements, hardware verification has become a critical bottleneck. The Verification Plan (vPlan) serves as the foundation for project success, enabling teams to prioritize critical tasks and maintain clear visibility into verification progress. Current vPlan development relies on manual attribute extraction from multiple specification documents, requiring engineers to meticulously infer test cases and coverage metrics. With limited timelines, this time-intensive process can result in plans containing gaps and suboptimal verification strategies, losing efficacy not being properly utilized. This thesis presents an automated framework that analyzes project documentation to extract Design Under Test (DUT) features and generate vendor-agnostic verification plans.