In advanced digital design, technology scaling permits reducing area, delay, and power of a system, but can increase susceptibility to radiation-induced soft errors, compromising system reliability. Soft errors can affect all logic blocks, with memory arrays being particularly vulnerable due to their high data density and charge-sensitive cells. Software crashes and computational errors may occur because of data corruption, leading to application faults. To mitigate this, system-level solutions such as Error Correction Codes are employed, adding redundancy bits to memory data. Extended Hamming code enables Single Error Correction and Double Error Detection with low area and latency overhead. However, in scaled SRAM, an exponential increase in the soft error rate can be observed because of multiple adjacent bit faults.