This thesis presents a structured methodology for testing and validating a hardware accelerator for TCUs, with a focus on fault coverage analysis using ATPG. The architecture under study consists of six DPUs designed for matrix multiplication in AI applications. The verification flow begins with RTL simulation in QuestaSim, followed by synthesis using Synopsys DC and gate-level validation to ensure functional equivalence. ATPG is conducted using Synopsys TetraMAX, applying SA fault models to assess test coverage. Specific configuration settings are used to generate deterministic patterns and export external test vectors for further analysis. A key contribution of this work is the classification and analysis of undetected faults, categorized as NC and NO.