As High-Performance Computing (HPC) advances towards the Exascale and Zettascale eras, energy efficiency has become a primary design objective. Relying only on transistor scaling to target peak performance is no longer sufficient. Higher clock frequencies correlates directly with higher dynamic power consumption, while operating voltage cannot be lowered without compromising performance target. This necessitates architectural optimizations to maximize Performance per Watt. In modern processors, especially in HPC system, the Floating-Point Unit (FPU) is the most common functional block. An analysis of the standard reference architecture of the Fused Multiply-Add (FMA) module, a critical component of the FPU, shows a clear inefficiency.