Vincenzo Olivieri
Exploration of High Level Synthesis for the Hardware Design of Digital Signal Processing Systems.
Rel. Giovanna Turvani, Fabrizio Riente, Giovanni Amedeo Cirillo. Politecnico di Torino, Master of science program in Electronic Engineering, 2025
Abstract
The continuously increasing complexity of digital hardware systems has led to a significant rise in design efforts, resulting in high costs in terms of time and resources. In Industry, the need to reduce time-to-market demands for increasing the productivity and requires methodologies capable of shortening development times without compromising the quality of products. In this context, High-Level Synthesis (HLS) emerges as an innovative and strategic solution, raising the level of abstraction in hardware design, overcoming the limitations of traditional manually-written Register Transfer Level (RTL) descriptions and automating hardware generation and verification. HLS translates algorithmic specifications written in high-level languages into optimized RTL descriptions, enabling designers to spend less time dealing with implementation details and to invest resources in algorithm development and system-level optimizations.
Nowadays, HLS is mainly applied to algorithm-dependent hardware design, like Digital Signal Processing (DSP) architectures
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