Design of an Advanced Register Renaming Architecture in a RISC-V Vector Processing Unit

Modeling and simulation are essential tools in science, enabling researchers toanalyze complex systems and predict their behavior. High Performance Computing (HPC) plays a crucial role by providing the computational power necessary to run large-scale simulations, driving breakthroughs across various scientific fields. For example, an ongoing challenge is climate modeling, which relies on HPC to predict and understand the effects of climate change, helping to guide global mitigation efforts. In addition, recent years have seen machine learning take on a growing role in technological development, enabling progress in areas such as audio and image processing, natural language processing, and autonomous driving. High-performance, efficient computing systems are essential for both training and real-time inference of these models. To address these challenges, computer architects have leveraged Data-Level Parallelism (DLP), a processing approach in which a single instruction operates on multiple data elements simultaneously. This results in improved performance and reduced demands on instruction and memory bandwidth, contributing to lower power consumption. A key implementation of DLP is found in vector processors, which feature two essential components: a vector register file (VRF), capable of holding a large number of elements, and multiple deeply pipelined functional units (FUs). To further enhance the performance of vector processors, design concepts from superscalar architectures can be applied. This is exemplified by the analyzed RISC-V-V 1.0 Vector Processing Unit (VPU), which features register renaming and lightweight out-of-order execution. This work details the complete design process, from conceptualization to RTL implementation, of an optimized register renaming mechanism. The mechanism introduces a new scheme for vector registers utilization in the execution of specific ISA instructions, leading to improvements in both performance and power efficiency. Its effectiveness is evaluated using state-of-the-art benchmarks from high performance computing and machine learning domains, analyzing trade-offs in power consumption and area.