Farida Saeidian Noghabi
Comprehensive analysis on different power integrity signoff methodologies and development of a novel flow with augmented coverage on critical timing paths.
Rel. Franco Fiori, Erica Raviola. Politecnico di Torino, Master of science program in Electronic Engineering, 2025
Abstract
The design and fabrication of Integrated Circuits (ICs) have become increasingly complex with the advancement of semiconductor technology and the move to smaller process nodes. As chip designs grow in scale and functionality, ensuring that a design is robust, reliable, and manufacturable becomes paramount. Sign-off in the semiconductor design process is the final stage of verification before a chip design is sent for manufacturing. It ensures the design meets all necessary specifications and quality requirements, avoiding costly errors in production. Sign-off typically involves a series of checks and analyses across different aspects of the design to guarantee functionality, reliability, and manufacturability.
Sign-off encompasses a variety of critical checks, including Static Timing Analysis (STA), Power Integrity (PI) verification, Signal Integrity (SI) checks, and physical verification steps such as Design Rule Check (DRC) and Layout Versus Schematic (LVS)
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