Andres Zambrano Bustos
ReCon Implementation: A Load Pair-Tracking Mechanism to Lift Security Protections on a RISC-V Processor.
Rel. Matteo Sonza Reorda. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2025
Abstract
Modern computer processors have become extremely complex, following Moore's law and growing the number of transistors exponentially through the years. As computer systems play increasingly critical roles in our daily lives, from simple tasks such as protecting personal data and passwords to managing global banking operations, safeguarding military secrets, and securing cryptocurrency keys; processors must ensure the highest levels of dependability and security. In recent years, the world has encountered new types of security risks known as "speculative side-channel attacks". These attacks exploit vulnerabilities in the time gap between the time when a processor executes an instruction and when it confirms the instruction's validity, exposing secret data, even that in so-called protected address space, and making it observable to an external party.
To address this security issue, mechanisms such as Non-speculative Data Access (NDA), Speculative Taint Tracking (STT), and Speculative Privacy Tracking (SPT) have been proposed
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