This thesis presents the design and implementation of a custom RISC-V core, which was developed as part of an internal research effort at Argotec, an Italian aerospace company. The primary objective of this work was to develop a RISC-V-based processor that could serve as a robust and flexible computing solution for future projects, particularly in the aerospace domain. The core was designed with an emphasis on providing a generic architecture that can be easily adapted and customized according to the specific requirements. ???? The implementation was based on the RV32I base version of the RISC-V instruction set architecture (ISA), which was selected for its simplicity and suitability for the targeted system.