Arianna Valenza
Study and Development of Optimised FPGA Manufacturing Tests Using On-Board processors in Rad-Hard Reconfigurable SoCs.
Rel. Luca Sterpone. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2025
Abstract
In the fast-paced landscape of the New Space Economy, companies are forced to accelerate time-to-market while keeping competitive pricing. This leads to an increasing demand for more efficient and flexible manufacturing processes, challenging traditional production methods. This thesis investigates an advanced approach to optimize the manufacturing testing procedures of Radiation Hardened by Design Field-Programmable Gate Arrays (FPGAs) embedded in System-on-Chip (SoC) devices, which can be adopted to support critical high-reliability aerospace missions and other demanding applications. The study aims to streamline traditional testing methods, which often prove complex and inflexible, by exploring the potential of using the onboard SoC processor for a light and adaptable test environment.
A proof-of-concept study on NanoXplore NG-Ultra was conducted to assess the feasibility of executing FPGA functional tests directly via the on-board ARM processor, focusing the research on testing the FPGA's configuration memory, a critical and fault-sensitive component fundamental for the device reliability and its nominal functioning
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