SNNs are one of the fastest-growing fields in neuromorphic computing and hold great potential for the next big revolution in energy efficiency, enabling both brain-like computing and real-time pattern recognition. Among these, the main challenges involve finding the best trade-off between power efficiency and area usage while preserving the accuracy and reliability of synaptic plasticity processes, such as Spike-Timing-Dependent Plasticity. The SNN architectures based on traditional CMOS technologies suffer from high power consumption and large areas; therefore, they are inappropriate to be deployed in a highly energy-constrained environment. Referring to these challenges, this work proposes an architecture of SNN on pure CMOS, designed and optimized using TSMC's 180 nm technology Cadence tool.