This thesis work explores new methodologies to be implemented with the aim of minimizing the time required to test the nonlinearity components in Analog-to-Digital Converters (ADCs), namely the Differential Nonlinearity (DNL) and the Integral Nonlinearity (INL). Traditional approaches to perform these measurements are the Ramp Histogram Test (RHT) and Sine Histogram Test (SHT) techniques. However, these methodologies are very time-consuming, especially when applied to high-resolution ADCs, as they require a significant number of samples to be acquired and consequently a considerable acquisition time. To address this limitation, this thesis work aims to investigate two possible algorithms for DNL and INL error evaluation by drastically reducing the number of samples required and even improving the accuracy of the measurements.