LUBIS EDA GmbH has the goal of creating software that aids engineers developing digital computing hardware, mainly in the field of formal verification. A software tool developed by the company produces formal properties from abstract system descriptions written in SystemC. In addition, it offers the Operation Level Synthesis (OLS), a feature which enables the generation of RTL designs based on the same system descriptions, which automatically fulfill those properties. The current state of the OLS directly outputs the resulting RTL design written in SystemVerilog without invoking any additional optimization tools. This thesis explores the possibility of supporting the hardware description language Chisel, which utilizes advantages of the programming language Scala, combining its object-oriented and functional programming features to enhance the RTL design process.