This thesis investigates experimentally various advanced techniques to achieve timing closure for the implementation of a new Base Band for Global Navigation Satellite System (GNSS) applications on Field Programmable Gate Array (FPGA). The introduction covers the theoretical background of GNSS and details the satellite information receiver system, specifically the Teseo chip by STMicroelectronics. The second chapter covers the analysis of the used hardware and the tools required to cover all the steps from the Hardware Description Language (HDL) implementation to the software used to validate the Base Band functional behavior. The implementation of the new Base Band (BB) will be covered, including HDL mapping and synthesis using Synplify for the targeted FPGA.