Study and implementation on FPGA of a new Baseband Datapath and Correlator for GNSS applications

This thesis investigates experimentally various advanced techniques to achieve timing closure for the implementation of a new Base Band for Global Navigation Satellite System (GNSS) applications on Field Programmable Gate Array (FPGA). The introduction covers the theoretical background of GNSS and details the satellite information receiver system, specifically the Teseo chip by STMicroelectronics. The second chapter covers the analysis of the used hardware and the tools required to cover all the steps from the Hardware Description Language (HDL) implementation to the software used to validate the Base Band functional behavior. The implementation of the new Base Band (BB) will be covered, including HDL mapping and synthesis using Synplify for the targeted FPGA. Implementation solutions were analyzed using Vivado to optimize the timing performance. After achieving the desired timing results, the bitstream was generated, and the FPGA’s functionalities were validated through emulation. I will present three Base Band designs: the CUT1 and CUT2 versions of the G6BB, followed by the G7BB design. An analysis of the G7BB with the STMicroelectronics design team was conducted to obtain a sufficiently small Worst Negative Slack (WNS), which could facilitate timing closure through further implementation optimizations. As can be evinced from the result of the implementations, CU2 has a 64.46% reduction of WNS with respect to CUT1; a +35.36% increase in the total power, and a 4.48%, 1.94%, 0.53%, and 1.93%, increases in the utilization of LUT, FF, DSP, and BUFG, respectively, which is coherent with the new features introduced and the variations performed. The optimization analysis was carried out for the CUT2. Here it was possible to see how it is design-dependent. The best results were achieved by using the retiming in Synplify and the Performance_ExplorePostRoutePhysOpt strategy in Vivado. This allows to achieve timing closure for CUT2, with an improvement of 100.03% in the WNS; a 30.46% reduction of total dissipated power; and 11.74%, 1.90%, 0.53%, and 1.89% increases in the utilization of LUT, FF, and DSP, respectively. Using the corresponding generated bitstream the validation led to the desired results. The initial design was iterated upon several times in collaboration with the design team, in order to improve the critical path performance. Using the Performance_ExplorePostRoutePhysOpt strategy in Vivado on the final release, the following improvements were obtained: an 88.07% reduction in WNS, a 5.69% decrease in total power dissipation, and increases in LUT utilization by 0.57% and FF utilization by 8.67%. Despite these advancements, the result remains sub-optimal with a WNS violation of -0.136 ns. Additionally, a WHS violation of -0.137 ns was found (also in the CUT2 implementation there was a Worst Hold Slack (WHS) violation of -0.148 ns). However, these violations are considered acceptable given that the constraints are intentionally pessimistic and slightly over-constrained to encourage the tool to apply a higher effort in resolving potential issues. Keeping this in mind, the generated bitstream was validated and the desired results were achieved.