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Analysis and Mitigation of Single Event Transients (SET) effect on RISC-V based FPGA

Aditya Garg

Analysis and Mitigation of Single Event Transients (SET) effect on RISC-V based FPGA.

Rel. Luca Sterpone. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2024

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Abstract:

In the rapidly evolving field of electronics, Field-Programmable Gate Arrays (FPGAs) have emerged as a cornerstone technology for a wide range of applications, from consumer electronics to critical aerospace systems. The versatility and programmability of FPGAs, combined with the increasing demand for low-power, high-performance computing, have led to the widespread adoption of Reduced Instruction Set Computing (RISC) architectures, notably the RISC-V, within FPGA designs. This open-source architecture offers significant advantages in terms of customization, scalability, and efficiency, making it an ideal candidate for integration into FPGA platforms. However, the deployment of RISC-V based FPGAs in radiation-prone environments, such as space, raises substantial reliability concerns due to the potential effects of radiation-induced errors. Radiation effects on semiconductor devices can lead to a myriad of operational challenges, including transient faults, permanent damage, and functional disruptions. For critical applications, these effects can compromise the integrity of the mission, endanger lives, and result in significant financial losses. Therefore, understanding the susceptibility of RISC-V based FPGA architectures to radiation is crucial for the development of effective mitigation strategies, ensuring reliability and functionality in adverse conditions. This thesis aims to delve into the intricate dynamics of radiation effects on NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) built around the open-source RISC-V compatible processor system that is written in platform-independent VHDL. Effects are studies by simulating single even transient, exploring the mechanisms behind radiation-induced failures and the implications for system reliability. By conducting a comprehensive analysis of these effects, this work seeks find ways to mitigate these effects by inserting additional circuits into the original circuit. In summary, as the use of RISC-V based FPGA architectures continues to expand into new frontiers, the significance of ensuring their reliability under radiation exposure cannot be overstated.

Relators: Luca Sterpone
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 66
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/31907
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