Starting with an RTL (Register Transfer Level) description of a SoC (System on Chip) is the first step towards developing a complete and functional product. This complex process, known as the Front-to-Back (Fe2Be) flow, encompasses a series of critical steps that aim to obtain a final working product. Timing constraints are the inputs for Static Timing Analysis (STA), which relies on them to assess if a circuit satisfies the necessary timing specifications for correct functioning. They play a crucial role in this transformation, as they are key to directing the logic synthesis process. The latter is a fundamental step in the digital implementation procedure, converting the RTL description into a digital logic network comprised of fundamental components such as AND gates, OR gates, adders, flip-flops and so on.