In recent years, quantum computing solutions have captured the interest of researchers and industries, fascinated by its computational superiority over classical systems, continuously developing new quantum algorithms. Nevertheless, validating these novel algorithms presents significant challenges, primarily due to constraints in qubit availability and the inherent noise in current quantum hardware. While software simulations present a solution, they often prove to be time-intensive. Consequently, hardware emulators are emerging as a promising alternative. This thesis proposes AMARETTO (quAntuM Architecture EmulaTion TechnOlogy) as a fast and efficient alternative for hardware emulation and verification of general-purpose quantum algorithms on low-tier Field-Programmable-Gate-Arrays (FPGAs), which are devices defined by relatively lower resource availability and cost-effectiveness.