Politecnico di Torino (logo)

AMARETTO, towards an efficient quantum emulation on Low-Tier FPGA

Christian Conti

AMARETTO, towards an efficient quantum emulation on Low-Tier FPGA.

Rel. Maurizio Zamboni, Mariagrazia Graziano, Giovanna Turvani, Deborah Volpe. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024

[img] PDF (Tesi_di_laurea) - Tesi
Restricted to: Repository staff only until 11 October 2025 (embargo date).
Licenza: Creative Commons Attribution Non-commercial No Derivatives.

Download (5MB)

In recent years, quantum computing solutions have captured the interest of researchers and industries, fascinated by its computational superiority over classical systems, continuously developing new quantum algorithms. Nevertheless, validating these novel algorithms presents significant challenges, primarily due to constraints in qubit availability and the inherent noise in current quantum hardware. While software simulations present a solution, they often prove to be time-intensive. Consequently, hardware emulators are emerging as a promising alternative. This thesis proposes AMARETTO (quAntuM Architecture EmulaTion TechnOlogy) as a fast and efficient alternative for hardware emulation and verification of general-purpose quantum algorithms on low-tier Field-Programmable-Gate-Arrays (FPGAs), which are devices defined by relatively lower resource availability and cost-effectiveness. AMARETTO supports Clifford+T and rotational gate sets, leveraging a Reduced-Instruction-Set-Computer (RISC)-like architecture for efficiently handling of sparse quantum gates unitary matrix. The Instruction-Set-Architecture of AMARETTO consists of three instruction types capable of configuring the emulator, executing gates, and retrieving processed data. The internal architecture of AMARETTO is technology-independent, enhancing its flexibility. This enables synthesis on any FPGA, with only the external interface requiring substitution to wrap the emulator and utilize the most available resources. The emulator utilizes a Single-Instruction-Multiple-Data (SIMD) datapath capable of concurrently processing various data, with the number of concurrent processes dependent on the resources of the FPGA. This also allows the implementation of embedded blocks found in modern FPGAs, such as memory, Digital-Signal-Processing (DSP) blocks, carry-chains, and fast multipliers. To verify the emulator's functionality, a metric named Great-Circle-Distance (GCD) has been defined. This metric can compute the distance of AMARETTO's result with respect to the golden model obtained using the Qiskit State Vector Simulator directly on the Q-Sphere surface. The entire AMARETTO ecosystem consists of the VHDL code representing the hardware itself, and a Python compiler for translating the quantum circuit described in OPENQASM 2.0 to the Instruction Set Architecture (ISA). Additionally, there is a driver capable of interfacing the programmable logic with the software, which depends on the specific FPGA and interface being utilized. Synthesis results are promising, demonstrating the ability to emulate seventeen qubits on a Xilinx Kria KV260 MPSoC, which rivals the best results currently described in the literature. Importantly, this achievement was attained using a small and affordable FPGA. This defines a novel approach to maximize the utilization of resources on cheaper FPGAs in the field of quantum emulation, highlighting how memory consumption is the unique bottleneck in the number of emulated qubits. Furthermore, the emulation time required for a quantum algorithm is significantly lower compared to software simulation. This brings real advantages in the execution and testing of iterative quantum algorithms, such as the Grover Adaptive Search which demands multiple emulation of a quantum circuit. This work results in the development of a complete emulation environment for fast and noiseless quantum circuits, which could be employed for validating quantum algorithms.

Relators: Maurizio Zamboni, Mariagrazia Graziano, Giovanna Turvani, Deborah Volpe
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 149
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/31115
Modify record (reserved for operators) Modify record (reserved for operators)