Pietro Fagnani
RTL UNR code analysis for verification closure applied to digital designs.
Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024
Abstract
Digital verification is an important part of integrated circuit development, ensuring that the design meets expected requirements and works correctly in all scenarios. This meticulous process involves a series of checks and tests that carefully examine the functionality, performance, and capability of the digital circuit. Through meticulous testing of the design across diverse conditions, engineers can detect and address any problems at an early stage in the development process. This approach prevents expensive revisions after production and guarantees the final product's reliability and quality. Coverage analysis is a fundamental aspect of digital verification, aimed at measuring the completeness of circuit testing.
Verification engineers need to go through all uncovered parts of the design and determine the reachability of the code before excluding it
Relatori
Anno Accademico
Tipo di pubblicazione
Numero di pagine
Informazioni aggiuntive
Corso di laurea
Classe di laurea
Aziende collaboratrici
URI
![]() |
Modifica (riservato agli operatori) |
