Lavinia Comerro
Optimizing FPGA Performance: Leveraging the Razor Technique in Digital Design.
Rel. Luciano Lavagno, Filippo Minnella. Politecnico di Torino, Master of science program in Electronic Engineering, 2024
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Abstract
As silicon integration technology advances and clock frequencies increase, optimizing power and reaching high performances has become crucial in developing Embedded Systems and Systems on Chip (SoC). Field-Programmable Gate Arrays (FPGAs) are semiconductors that offer high flexibility as they can be reprogrammed after manufacturing, offering lower design cost and customization for specific applications. However, this flexibility comes at a price - FPGAs are less performance and energy efficient. Therefore, to achieve significant performance improvements, it is necessary to rely on architectural modifications and technology scaling of digital designs to operate beyond conventional safety limits. Typically, FPGA systems provide large timing guard bands during the design phase to guarantee safe operation across manufacturing and design.
In order to achieve the demand power and performance levels, it is feasible to operate above these limits, acknowledging the possibility of errors occurring within the design and then implementing a technique for error detection and correction
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