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Test Pattern Bring-up for First Silicon Debug of 800G Optical Modules

Ali Moaz

Test Pattern Bring-up for First Silicon Debug of 800G Optical Modules.

Rel. Mario Roberto Casu, Nicola Carta. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024


This thesis presents an innovative exploration of the initial debugging process for newly developed semiconductor silicon, focusing particularly on the 800G optical modules. Given the complex nature of semiconductor production, efficient strategies for first silicon bring-up and debugging are crucial to ensure the successful operation of these devices. This study delves into the intricacies of this process, primarily the challenges associated with Automatic Test Pattern Generation (ATPG) patterns and the use of Automatic Test Equipment (ATE) systems. It dives deep into the world of high-speed communication, focusing on the challenges of the first silicon debug in optical modules that operate at a whopping 800G. With technology constantly racing ahead, there's a pressing need to test and debug new devices efficiently. To this end, we've explored and developed a system that can communicate with the Spica Gen2 platform, sending it test patterns and analyzing the results. We've harnessed the power of tools like Tessent for creating these test patterns. Through our research, we aim to make the silicon bring-up process smoother, ensuring that the next generation of high-speed devices is reliable and top-notch.

Relators: Mario Roberto Casu, Nicola Carta
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 102
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: MARVELL TECHNOLOGY ITALY S.R.L.
URI: http://webthesis.biblio.polito.it/id/eprint/30940
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