The design and optimization of a Network on-chip (NoC) for efficient communication in System-on-Chip (SoC) architectures pose a complex challenge. It involves balancing diverse requirements such as low latency, high bandwidth, and energy efficiency while managing the increasing complexity and heterogeneity of on-chip components. One of the most serious challenges is how to allocate the different computational workloads in the compute units of the NoC. The allocation process has a major impact on power consumption, performance, and of hardware resources required for correct, routing, and parallelization. Additionally, poor Network-on-Chip (NoC) design can lead to system deadlocks or livelocks, highlighting the need for more efficient and robust communication architectures in System-on-Chip (SoC) systems.