Memories are macros with many pins and paths, so they play a critical role in static timing analysis. Due to their numerous and short paths, they are prone to a significant number of hold time violations in specific scenarios with high-voltage. Since even Concurrent Clock and Data (CCD) Optimization technology offered by PNR tools have poor results in solving this problem, this work explores new systematic approaches based on useful skew technique. Useful skew in physical design refers to a deliberate introduction of controlled delay imbalances among clock signals in integrated circuits. This technique helps to improve the timing and performance of high-speed digital design.