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Design of an integrated voltage regulator for low-power applications

Davide Guzzetta

Design of an integrated voltage regulator for low-power applications.

Rel. Fabio Pareschi, Nicolò Zilio. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

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This thesis work has been developed in the field of analog design, in particular in power management applications. The work consisted in the re-design of a low dropout voltage regulator, device belonging to the category of the DC-DC converters. The focus was on the implementation of an innovative method of biasing of the circuit's devices, which made the bias current dependent on the output load current instead of constant, with considerable effects on the consumption and the performance. All the considerations on the design were made taking into account the bias current variations, the stability, the bandwidth and the power supply rejection, which is one of the most important parameters of a voltage regulator. The challenge of developing this thesis were the really low available supply voltage, which is one of the main limits in the analog design, and reaching the performance goal allowing to make the circuit actually suitable for the implementation on a real integrated circuit.

Relators: Fabio Pareschi, Nicolò Zilio
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 104
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Infineon Technologies Austria AG
URI: http://webthesis.biblio.polito.it/id/eprint/29529
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