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Definition and implementation of new FIR instruction integrated in RISC-V ISA for audio applications

Paolo Andrea Romeo

Definition and implementation of new FIR instruction integrated in RISC-V ISA for audio applications.

Rel. Mario Roberto Casu, Michele Chiabrera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023


With the increasing presence of audio smart amplifiers into daily-lives applications that go from mobile phone, virtual assistants and podcast to gaming and automotive environment, the demand of an improvement and optimization of audio quality has grown, contributing to a growing research of new technological innovations both in software and hardware. A central topic for smartPA is to maximize the power delivered to speakers by avoiding damages to it. For this reason, much effort has been made for the development of an efficient speaker protection algorithm able to avoid specific issues like the speaker-membrane excursion and the rising of its temperature above a certain threshold. This thesis project (developed in Inventvm S.R.L, an Italian fabless company situated in Pavia) starts from an existing SW algorithm running on RISC-V based platform. The activity is part of a larger project that aims to reduce algorithm execution time by including custom instructions in the RISC-V ISA. In particular, this thesis focused on the design and implementation of a FIR (Finite Impulse Response) instruction for audio samples processing. As a matter of fact, by analysing the RISC-V structure, it has been possible to create an instruction coherent and compatible with the ones already present in the Instruction Set. This operation was done by re-using already existent logic, such as multipliers, to guarantee a negligible area increasing in RISC-V core. As a result, the usage of custom instructions proved that the execution of a speaker protection algorithm is more efficient compared with a SW solution using standard RISC-V instructions. This implementation led to a significant enhancement in terms of execution time with a negligible increasing of area, establishing that the hardware path taken is likely to represent the right way.

Relators: Mario Roberto Casu, Michele Chiabrera
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 112
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: INVENTVM Semiconductor SRL
URI: http://webthesis.biblio.polito.it/id/eprint/28684
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