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Study and testing of a processor for Embedded Systems in the new space era

Giommaria Pilo

Study and testing of a processor for Embedded Systems in the new space era.

Rel. Luca Sterpone, Eleonora Vacca, Sarah Azimi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

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The world is entering now in a new era of space exploration. Launch costs have reduced significantly and the number of actors launching satellites into orbit will continue to increase. New projects for satellite launches, and exploration missions require always increasing levels of performance and reliability from electronic components. Due to the high level of radiation present in space environments, the incidence of Single Event Transient and Single and Multiple Event Upsets is really high for digital circuits and can easily cause disruption of the system mission. This thesis work focuses on a new soft-core to implement on a Field Programmable Gate Array, developed by an Italian company, focused on reaching the highest level possible of reliability, without need of external maintenance, the Rempro. The processor features both Radiation Hardening by Process and Radiation Hardening by Design techniques to increase fault tolerance. Since it targets flash-based FPGAs, it is immune to Single Event Upsets. Moreover the project uses Triple Module Redundancy at the core level and N Module Redundancy at the system level, allowing for automatic substitution and reconfiguration of the faulty triplets when a malfunction is detected. This makes the system incredibly resilient and capable of preserving the execution of its task effectively even after being affected by multiple faults. A bus was developed as well as a transmission and memory recovery protocol in order for the processor to be able to transmit its program state to a new one, when it must be replaced. The new features were validated in three implementation tests to insure that the memory recovery process worked as intended. Finally the processor was compared to a state of the art RISC-V processor, the NEORV32, in terms of fault tolerance by means of a fault injection campaign. Three benchmark programs were developed for the two processors as well as a framework for the fault injection. Data was gathered from the campaign to highlight the criticalities of the design, in order to focus future work on the improvement of the project.

Relators: Luca Sterpone, Eleonora Vacca, Sarah Azimi
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 102
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: IES srl
URI: http://webthesis.biblio.polito.it/id/eprint/28517
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