Testing and verification of integrated circuits (ICs) is a vital process to ensure they meet performance standards. IC manufacturing can introduce various physical irregularities, including transistor issues and short circuit connections, leading to operational misbehaviors. Test generation aims to find stimuli that uncover these defects while applied to the inputs of the IC, and fault models provide a framework for the process. Various fault models have been implemented over the years which try to simulate different possible defects in the structure of IC. Stuck-at and Transition delay fault models are the two traditional fault models widely used. Other models such as Path delay faults and Cell-aware faults have been defined and utilized which take into consideration the defects possible in a lower level.